Title :
Scaling of CMOS FinFETs towards 10 nm
Author :
Chen, Hao-Yu ; Huang, Chien-Chao ; Huang, Cheng-Chuan ; Chang, Chang-Yun ; Yeo, Yee-Chia ; Yang, Fu-Liang ; Hu, Chenming
Author_Institution :
Taiwan Semicond. Manuf. Co. Ltd., Hsin-Chu, Taiwan
Abstract :
CMOS FinFETs with 35 nm gate length Lg and performance parameters exceeding that of ITRS projections are fabricated. Device simulations are performed to match the experimental results and to explore the scalability and optimization of FinFETs to 10 nm gate length. Symmetrical NMOS and PMOS Vt´s, low off-state leakages, and high drive currents can be realized using dual-doped poly-Si or mid-gap gate electrodes.
Keywords :
CMOS integrated circuits; MOSFET; elemental semiconductors; leakage currents; nitrogen; phosphorus; semiconductor device models; silicon; sputter etching; 19 nm; 35 nm; CMOS FinFET; NMOS transistor; PMOS transistor; Si:N,P; device simulation; drive currents; dual-doped poly-Si; gate length; leakage current; mid-gap gate electrodes; optimization; scalability; Annealing; Electrodes; Etching; Fabrication; FinFETs; Immune system; MOS devices; Oxidation; Semiconductor device modeling; Silicides;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252548
