Structural demonstration of cost effective isolation trench fill for sub-110 nm vertical trench DRAM and SOC applications

A highly manufacturable voids-free Isolation Trench (IT) fill scenario was developed to address the critical challenge of forming high Aspect Ratio (AR) device isolation in 110 nm vertical DRAM [1,2]. We successfully demonstrated the fill of array and support isolation trenches with gap fill AR more than 6 by a simple combination of LP-TEOS and HDP oxide. The proposed scheme offers reduced thermal budget, high throughput, and minimized added complexity compared to multiple-steps HDP-filled or O₃-TEOS-filled Shallow-Trench-Isolation (STI). We found a perfect match in manufacture of low-cost inter-wells isolation for System-On-A-Chip (SOC) in addition to vertical DRAM fabrication.