Circuit design issues for the POWER4 chip

POWER4 is a next-generation system-on-a-chip design, incorporating two microprocessor cores, 1.44 MB L2 memory, and L3 directory and memory controller, all on one die.[1-3] It contains over 170 million transistors, and operates at frequencies in excess of 1.3 GHz in IBM\´s 0.18 μm silicon-on-insulator (SOI) technology.[4] Along with the usual area, power, and frequency concerns, the circuit design leaders of this chip faced many difficult and, in some cases, unique challenges including the definition and application of global clocking and latching styles, rigorous definitions of allowed circuit styles, rules, and methodologies, and special considerations for SOI-related phenomena. The circuit design "rules and regulations" had to be carefully crafted and balanced to allow achievement of the project\´s aggressive design goals, while at the same time taking the utmost care to minimize the risks imposed by the size of the chip and its logical complexity, new features, aspects and characteristics of the SOI technology, the number of designers involved and their varying levels of skill and experience, and the necessity of maintaining strict adherence to a tight product delivery schedule. This paper describes the circuit design of the POWER4 chip, covering in detail some of the solutions adopted, as well as the techniques and methodologies employed to optimize the design.