A new timing-driven standard cell placement algorithm

This paper proposes a new timing-driven standard cell placement algorithm. This algorithm uses the sum of the maximum timing delay of all nets in the circuit as the cost function. A weight is assigned to each net according to the sum of the criticality of the paths that pass through the net. We combine the proposed timing-driven cost function with the quadrisection based partition algorithm to obtain a placement to have a shorter timing delay of the circuit. The experiments show that applying the criticality of the paths to nets improves the timing delay of the circuit. We modify the cost function to use the half perimeter of a net and compare the timing delays generated by these two cost functions. Results are show in the paper. The program has been integrated in a commercial design flow.