Title :
Simultaneous routing and buffering in floorplan design
Author :
Fang, Jyh Perng ; Tong, Yung-Shan ; Chen, Sao Jie
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
To deal with the floorplan design in a system-on-chip (SOC), we have developed an EDA tool that simultaneously considers the problems of routing and buffer-insertion in floorplanning. This routing and buffering tool mainly contains a manhattan routing (MR) algorithm and a maze-based between-buffer routing (MBR) algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.
Keywords :
VLSI; buffer circuits; circuit layout; electronic design automation; network routing; system-on-chip; EDA; SOC; buffer insertion; electronic design automation; floorplan design; iterative floorplanning algorithm; manhattan routing algorithm; maze based between buffer routing algorithm; system-on-chip; Delay estimation; Design engineering; Electronic design automation and methodology; Iterative algorithms; Modems; Phase estimation; Routing; System-on-a-chip; Tiles; Upper bound;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252584
