DocumentCode :
2395095
Title :
A re-configurable architecture--radio processor
Author :
Liao, I-Tao ; Lee, Tse-Hao ; Kang, Chung-Chieh ; Shih, Chia-Hung ; Tsai, Jia-Cheng ; Lai, Hung-Chi ; Shen, Jian-Hui ; Liu, Chih-Wei
Author_Institution :
Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear :
2003
fDate :
6-8 Oct. 2003
Firstpage :
200
Lastpage :
203
Abstract :
The radio processor (RP) is a heterogeneous configurable computing subsystem, which is designed to perform layer 1 functions within different communication systems. The features of radio processor include (1) heterogeneous configurable architecture, (2) scalable infrastructure with unified design environment, (3) customizable design, (4) flexible instruction set, and (5) limited main-processor resource requirement.
Keywords :
hardware-software codesign; reconfigurable architectures; system-on-chip; customizable design; flexible instruction set; heterogeneous configurable computing subsystem; limited main processor resource requirement; radio processor; reconfigurable architecture; scalable infrastructure; Application software; Computer aided instruction; Computer architecture; Costs; Energy consumption; Hardware; Heart; Microprocessors; Signal processing; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
ISSN :
1524-766X
Print_ISBN :
0-7803-7765-6
Type :
conf
DOI :
10.1109/VTSA.2003.1252587
Filename :
1252587
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2395095
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