Title :
CMOS design techniques for 10 Gb/s optical transceivers
Author :
Green, Michael M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Abstract :
This paper presents design techniques used for high-speed CMOS broadband circuits operating at high bit rates. Optimal design and biasing of CMOS CML structures are discussed, and the method of shunt-peaking is presented. Designs of 10 Gb/s multiplexer and demultiplexer are described.
Keywords :
CMOS logic circuits; current-mode logic; demultiplexing equipment; integrated circuit design; multiplexing equipment; transceivers; 10 GB/s; CMOS CML structures; CMOS design; complementary metal oxide semiconductor; current-mode logic; demultiplexer design; high speed CMOS broadband circuits; multiplexer design; optical transceivers; shunt peaking inductors; CMOS logic circuits; CMOS technology; Capacitance; Logic circuits; MOSFETs; Optical design; Optical design techniques; Tail; Transceivers; Voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252590
