Title :
A 144dB, 8.5mW fourth-order single loop delta-sigma modulator
Author :
Zare-Hoseini, Hashem ; Farazian, Mohammad ; Shoaei, Omid
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
In this paper a 144dB, fourth-order single-loop delta-sigma modulator has been presented with an over-sampling ratio of 1024 and an overload factor of -1.24 dB for a bandwidth of 1000 Rad/s with a new low power integrator in the front-end of the modulator. In this integrator two large mismatch-free capacitors are well embedded to strongly attenuate the input sampling (KT/C) noise without using any large sampling or integrating capacitors. Therefore, the first integrator can be easily designed with a little power and area consumption. Also CDS used in the front-end integrator strongly reduces the 1/f noise and cancels out op-amp´s offset. The whole modulator consumes only 8.5 mW from a single 3.0V supply in a 0.6-μm CMOS technology.
Keywords :
1/f noise; CMOS integrated circuits; capacitors; delta-sigma modulation; interference suppression; low-power electronics; modulators; power consumption; 0.6 micron; 144 dB; 3 V; 8.5 mW; CMOS technology; capacitors; fourth order single loop delta sigma modulator; front end integrator; noise reduction; power consumption; power integrator; sampling ratio; Bandwidth; CMOS technology; Capacitors; Delta modulation; Filters; Frequency; Low-frequency noise; Noise cancellation; Operational amplifiers; Sampling methods;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2003 International Symposium on
Print_ISBN :
0-7803-7765-6
DOI :
10.1109/VTSA.2003.1252593
