Analytical expression for signal propagation delay of off-chip interconnection for SIP application

Author

Owzar, Amir ; Mueller, Kurt ; Baykal, Ertan ; Stephan, Ralph ; Helfenstein, Markus

Author_Institution

NXP Semicond., Zurich

fYear

2007

fDate

Oct. 29 2007-Nov. 1 2007

Firstpage

848

Lastpage

851

Abstract

A new analytical expression is propossed for the calculation of the delay time of off-chip pin-to-pin interconnection. This includes all the line and the load parameters for CMOS based circuits. The classical on-chip analytical formulations available in the literature have been reviewed. Spice simulations are applied to compare the accuracy of the proposed expressions. Measurement results have been used for the determination of the accuracy of the spice line model.

Keywords

CMOS integrated circuits; integrated circuit interconnections; CMOS circuits; Elmore delay; SIP application; analytical expression; line inductance; load impedance; off-chip interconnection; pin-to-pin interconnection; signal propagation delay; Delay effects; Electrical resistance measurement; Impedance; Inductance; Length measurement; Propagation constant; Propagation delay; Signal analysis; Solid modeling; Transmission line measurements; Elmore delay; Load impedance; chip-to-chip wire; line inductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Optoelectronics Conference, 2007. IMOC 2007. SBMO/IEEE MTT-S International

Conference_Location

Brazil

Print_ISBN

978-1-4244-0661-6

Electronic_ISBN

978-1-4244-0661-6

Type

conf

DOI

10.1109/IMOC.2007.4404390

Filename

4404390