DocumentCode
2395421
Title
An illustration of specification modeling with VHDL using a Futurebus+ model
Author
Izzo, Peter A.
Author_Institution
Protocol Services Div., Zycad, Rockaway, NJ, USA
fYear
1994
fDate
30 Oct-3 Nov 1994
Firstpage
556
Lastpage
560
Abstract
This paper outlines a VHDL-based modeling methodology targeted towards the class of bus functional models that are described by a comprehensive specification. It discusses the basic modeling approach of a specific specification model, a Futurebus+ system model. In addition, the behavioral design of a portion of the system model is illustrated
Keywords
formal specification; hardware description languages; system buses; Futurebus+ model; VHDL; behavioral design; bus functional models; modeling; specification modeling; system model; Backplanes; Centralized control; Control system synthesis; Engineering management; Logic testing; Natural languages; Power system modeling; Protocols; System testing; Systems engineering and theory;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital Avionics Systems Conference, 1994. 13th DASC., AIAA/IEEE
Conference_Location
Phoenix, AZ
Print_ISBN
0-7803-2425-0
Type
conf
DOI
10.1109/DASC.1994.369424
Filename
369424
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