VLSI interconnects at multi GHz frequencies incorporating inductance

Due to decreasing device sizes and increasing clock speed, the interconnect delay is the dominant factor in clock skew. This delay has been extracted as RC component in available EDA tools. In this paper, we model the interconnect as RLC for systems running at multi-GHz. A static extraction analysis method optimized for VLSI is detailed which considers all lines within the vicinity of the target line as return paths. Novel formulas presented for parallel and series RLC reduction. Result characterization and future research areas are discussed.