A 5-GHz CMOS front-end circuit with low power, low noise and variable gain for WLAN applications

Author

Lin, Min ; Li, Yongming ; Chen, Hongyi

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2003

fDate

2003

Firstpage

280

Lastpage

283

Abstract

Incorporating the low-IF architecture, a 5-GHz WLAN receiver front-end chip is implemented in a 0.18 μm CMOS technology. The chip contains a single-in differential-out low noise amplifier with 1.5 dB noise figure (NF), 25 dB voltage gain and less than 13 mW power consumption, a folded structure downconversion mixer with 9.9 dB single side band noise figure (SSB NF), 13.7 dB voltage gain and+2.7 dBm IIP3, consuming 10 mA current under a 2V supply voltage. The chip also has a 12 dB gain adjustment through a VGA cell placed in parallel with LNA´s input.

Keywords

CMOS analogue integrated circuits; differential amplifiers; integrated circuit noise; low-power electronics; microwave amplifiers; microwave integrated circuits; microwave mixers; radio receivers; wireless LAN; 0.18 micron; 1.5 dB; 10 mA; 12 dB; 13.7 dB; 2 V; 25 dB; 5 GHz; 9.9 dB; CMOS front-end circuit; WLAN applications; WLAN receiver front-end chip; folded structure downconversion mixer; low power amplifier; low-IF architecture; power consumption; radio receivers; single side band noise figure; single-in differential-out low noise amplifier; variable gain amplifier cell; CMOS technology; Circuit noise; Differential amplifiers; Energy consumption; Gain; Low-noise amplifiers; Noise figure; Noise measurement; Voltage; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2003 International Symposium on

ISSN

1524-766X

Print_ISBN

0-7803-7765-6

Type

conf

DOI

10.1109/VTSA.2003.1252608

Filename

1252608