DocumentCode
2395470
Title
A flexible resampling mechanism for parallel particle filters
Author
Hong, Sangjin ; Chin, Shu-Shin ; Magesh, Sadasivam
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
fYear
2003
fDate
2003
Firstpage
288
Lastpage
291
Abstract
This paper presents an efficient flexible resampling architecture for parallel particle filtering. The architecture incorporates distributed, delayed resampling mechanisms for fast resampling processing. The architecture consists up to four resampling units and 16 processing elements. Their interconnection can be dynamically reconfigured. The architecture is designed and evaluated for bearing tracking example. The architecture is designed for 0.25 μm CMOS technology.
Keywords
CMOS integrated circuits; VLSI; integrated circuit interconnections; nonlinear filters; signal sampling; tracking filters; 0.25 micron; CMOS technology; delayed resampling; distributed resampling; flexible resampling architecture; integrated circuit interconnections; parallel particle filters; tracking filters; CMOS technology; Computer architecture; Concurrent computing; Delay effects; Design engineering; Filtering; Hardware; Laboratories; Mobile computing; Particle filters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2003 International Symposium on
ISSN
1524-766X
Print_ISBN
0-7803-7765-6
Type
conf
DOI
10.1109/VTSA.2003.1252610
Filename
1252610
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