Ultra-Low-Power Cascaded CMOS LNA With Positive Feedback and Bias Optimization

A novel circuit topology for a CMOS low-noise amplifier (LNA) is presented in this paper. By employing a positive feedback technique at the common-source transistor of the cascade stage, the voltage gain can be enhanced. In addition, with the MOS transistors biased in the moderate inversion region, the proposed LNA circuit is well suited to operate at reduced power consumption and supply voltage conditions. Utilizing a standard 0.18-μm CMOS process, the CMOS LNA has been demonstrated for 5-GHz frequency band applications. Operated at a supply voltage of 0.6 V, the LNA with the gain-boosting technique achieves a gain of 13.92 dB and a noise figure of 3.32 dB while consuming a dc power of 834 μW. The measured P_1-dB and input third-order intercept point are -22.2 and -11.5 dBm, respectively