An All Digital CMOS Serial Link Transceiver with 3x Over-sampling Based Data Recovery

Author

Wang, Zhijun ; Liang, Liping

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

fYear

2006

fDate

Dec. 2006

Firstpage

15

Lastpage

19

Abstract

An all digital CMOS serial link transceiver with 3x over-sampling based data recovery circuit is presented in this paper. The modified data recovery circuit is simpler than those using 3x over-sampling recovery circuit in (Chih-Kong Ken Yang et al., 1998) and (Chih-Kong Ken Yang and Horowitz). An all digital DLL (delay locked loop) is used to generate the multiphase clocks and a new CPRD (coarse phase-difference range decision) unit is introduced here to reduce the lock time. The whole design´s feasibility is verified by the Verilog HDL modeling. And the DLL´s performance is simulated by HSPICE in SMIC 0.18mum CMOS technology. The simulation results show that the system is workable. The data recovery´s latency of the transceiver is reduced to 5 cycles and the whole system can hold about 1Gbps data bit rate in the worst case

Keywords

CMOS digital integrated circuits; SPICE; clocks; delay lock loops; hardware description languages; signal processing equipment; transceivers; 0.18 micron; CMOS technology; HSPICE; Verilog HDL modeling; coarse phase-difference range decision unit; digital CMOS serial link transceiver; digital delay locked loop; multiphase clocks; over-sampling based data recovery circuit; Bit rate; CMOS digital integrated circuits; CMOS technology; Clocks; Delay; Frequency; Hardware design languages; Real time systems; System-on-a-chip; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, The 6th International Workshop on

Conference_Location

Cairo

Print_ISBN

1-4244-0898-9

Type

conf

DOI

10.1109/IWSOC.2006.348256

Filename

4155252