Architectural Design and Implementation of an FPGA Softcore Based Speech Recognition System

In spite of ever increasing logic capacity of FPGAs, the implementation of a large vocabulary speech recognition system encounters insufficient I/O bandwidth and internal memory capacity problems. In this paper, a speech recognition system architecture was described based on a softcore with hardware accelerators for the emission probability computation and the Viterbi beam search. The hardware accelerator for emission probability computation is equipped with the internal memory to effectively capture the access pattern of the acoustic model data which depend on the language model. The optimal memory configuration is determined by the proposed data partitioning strategy. The developed system has been implemented on a Xilinx Virtex-4 FPGA with MicroBlaze softcore processor along with various peripherals. The experimental results show that the proposed architecture speeds up the recognition by reducing the memory bandwidth requirement thereby the system is capable of performing real-time recognition for the DARPA resource management task which supports about 1000 words continuous speech recognition