A Delay Model for Networks-on-Chip Output-Queuing Router

Routers are vital modules in any networks-on-chip (NoC)-based design. To achieve an adequate performance, routers must be designed to match network inter-module traffic. One of the most important methods to accomplish this matching is to minimize the router delay. An early estimation of the router delay is critically needed to help designers specify the system timing constrains at higher levels of abstraction. In this paper, we present a delay model for NoC routers and explain how it can be used to study the effect of changing the queue size and the number of ports on the router delay and throughput. The novelty in our model is that it can be applied to techniques that use both clock edges to achieve low latency and, hence, improve the performance. The proposed model returns the router delay in terms of number of clock cycles as a technology-independent representation