Title :
On-Line Test Vector Generation from Temporal Regular Expressions
Author :
Oddos, Yann ; Morin-Allory, Katell ; Borrione, Dominique
Author_Institution :
Tima Lab., Grenoble Cedex
Abstract :
The authors propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a SERE formula, the authors build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation
Keywords :
automatic test pattern generation; field programmable gate arrays; hardware description languages; FPGA; SERE formula; automatic generation test vectors; on-line test vector generation; property specification language; random temporal test vectors; synthesizable generator; temporal regular expressions; verification platforms; Algorithm design and analysis; Automatic testing; Circuit testing; Field programmable gate arrays; Hardware design languages; Laboratories; Real time systems; System testing; System-on-a-chip; Writing;
Conference_Titel :
System-on-Chip for Real-Time Applications, The 6th International Workshop on
Conference_Location :
Cairo
Print_ISBN :
1-4244-0898-9
DOI :
10.1109/IWSOC.2006.348223
