DocumentCode :
2396025
Title :
Intelligent Fill Pattern and Extraction Methodology for SoC
Author :
Balasinski, Artur ; Cetin, Joseph
Author_Institution :
Cypress Semicond., San Diego, CA
fYear :
2006
fDate :
Dec. 2006
Firstpage :
156
Lastpage :
159
Abstract :
Uniform pattern density of physical layers of the die, such as diffusion, poly, or metals, has significant impact on electrical parameters of the product. At active level, variations in pattern density across the die translate into wide distributions of punch-through or breakdown voltages. At poly and metal levels, a non-uniform pattern density would result in poor planarity and give rise to high via resistances and poor control of the inter-layer capacitive coupling. However, at design stage, the complex functions of SoC functional blocks do not give designers enough freedom to strictly observe a predefined set of pattern density rules. Instead, the die pattern has to be made more uniform at die integration level, by global addition of fill features (waffles). While conceptually simple, this presents significant technical challenge, as the criteria for this addition are often difficult to meet. The simple but time consuming way of making pattern density uniform is based on manual drawing of dummy features over the electrical database (intellectual property, IP) of the die. A simplistic, automated approach is to add fill pattern of fixed density until it becomes close to target pattern density of the die. However, it may not be possible to equalize out all the regions even with changes in the die architecture. In addition, this approach tends to add dummy features even if unnecessary, driving towards very high pattern density. This solution is disadvantageous for RF/analog products the performance of which can be compromised by the capacitive coupling through the waffles. The methodology proposed that the initial die pattern density is first evaluated followed by the adjustable, intelligent fill of dynamic density at the block level. This way, it is possible to keep the original pattern density and work only on the areas of small density. The authors propose that the standard cell methodology should enable pre-die level modifications of pattern density and its extra- ction, to ensure that all the required blocks could be placed on the product and that their parasitics are properly extracted
Keywords :
coupled circuits; electric breakdown; industrial property; system-on-chip; SoC; analog products; breakdown voltages; die pattern; electrical database; electrical parameters; extraction methodology; intellectual property; intelligent fill pattern; inter-layer capacitive coupling; radiofrequency products; Conferences; Contact resistance; Etching; Intellectual property; Isolation technology; Physical layer; Planarization; Radio frequency; Real time systems; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip for Real-Time Applications, The 6th International Workshop on
Conference_Location :
Cairo
Print_ISBN :
1-4244-0898-9
Type :
conf
DOI :
10.1109/IWSOC.2006.348227
Filename :
4155280
Link To Document :
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