• DocumentCode
    2396103
  • Title

    Complex-argument universal nonlinear cell for rapid prototyping wafer architecture

  • Author

    Lin, L. ; Jain, V.K.

  • Author_Institution
    Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
  • fYear
    1995
  • fDate
    18-20 Jan 1995
  • Firstpage
    12
  • Lastpage
    21
  • Abstract
    The development of generic cells to perform linear and nonlinear arithmetic is critical to successful WSI implementations of signal and image processing algorithms. Our WARP wafer architecture deploys generic cells, thereby offering the capability of mapping a wide variety of computational algorithms on to the same pool of resources. This paper presents a further advance in this direction. Specifically, it reports on the development of a complex-argument nonlinear universal cell. A 16 bit chip and its application to WSI signal processing algorithms are discussed. In particular, an antenna array processing algorithm is discussed which is amenable to mapping to the WARP wafer
  • Keywords
    CMOS digital integrated circuits; VLSI; array signal processing; digital signal processing chips; parallel algorithms; parallel architectures; pipeline arithmetic; wafer-scale integration; 16 bit; WARP wafer architecture; WSI implementations; WSI signal processing algorithms; antenna array processing algorithm; complex-argument universal nonlinear cell; generic cells; rapid prototyping wafer architecture; Arithmetic; Array signal processing; Computer architecture; Image processing; Interpolation; Joining processes; Laser beam cutting; Prototypes; Signal processing; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-2467-6
  • Type

    conf

  • DOI
    10.1109/ICWSI.1995.515434
  • Filename
    515434