Title :
FPGA-Based Low-level CAN Protocol Testing
Author :
Mostafa, M. ; Shalan, M. ; Hammad, S.
Author_Institution :
Mentor Graphics, Cairo
Abstract :
The paper proposes a new approach for testing a CAN bus at the bit-level. It depends on generation of bus errors to cover crucial corner cases. The design makes it possible to go beyond regular frame level testing that is provided by many commercial tools. It goes deep in bit-stream level testing and injection. The proposed design is verified using an FPGA system on chip. Verification results are good against design requirements
Keywords :
controller area networks; field programmable gate arrays; protocols; system-on-chip; CAN bus; FPGA; automotive testing; bus error generation; low-level protocol testing; system on chip; Automotive engineering; Electrical equipment industry; Error correction; Field programmable gate arrays; Hardware; Monitoring; Protocols; System testing; System-on-a-chip; Transmitters; Automotive Testing; CAN; FPGA;
Conference_Titel :
System-on-Chip for Real-Time Applications, The 6th International Workshop on
Conference_Location :
Cairo
Print_ISBN :
1-4244-0898-9
DOI :
10.1109/IWSOC.2006.348233
