A framework for fair performance evaluation of 1-bit full adder cells

Evaluating the performance measures of a full adder (FA) cell depends on the input test pattern, and on the circuit structure used for simulation. The issue gets more complicated when evaluating several parameters such as time delay, area, power dissipation, and driving capability at the same time. In this paper a framework for evaluating and comparing 1-bit FA cells is proposed. The framework consists of an input test pattern which can give accurate speed, and power consumption figures, plus two circuit simulation structures that test the performance of adder cells in a proper context. 25 different full adder cells, collected from the literature, are evaluated and ranked using the proposed framework, which ensures fair comparison basis