DocumentCode :
2396731
Title :
Implementation of artificial neural networks on a reconfigurable hardware accelerator
Author :
Porrmann, Mario ; Witkowski, Ulf ; Kalte, Heiko ; Rückert, Ulrich
Author_Institution :
Heinz Nixdorf Inst., Paderborn Univ., Germany
fYear :
2002
fDate :
2002
Firstpage :
243
Lastpage :
250
Abstract :
The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementation issues are considered. In particular, the resource efficiency and performance of the presented realizations are discussed
Keywords :
content-addressable storage; field programmable gate arrays; neural chips; neural net architecture; performance evaluation; radial basis function networks; reconfigurable architectures; self-organising feature maps; FPGA-based system; RAPTOR2000; artificial neural networks; basis function networks; hardware implementation; implementation issues; neural architectures; neural associative memories; performance; reconfigurable hardware accelerator; resource efficiency; self-organizing feature maps; system-on-chip; Acceleration; Artificial neural networks; Broadcasting; Field programmable gate arrays; Memory management; Neural network hardware; Postal services; Prototypes; Random access memory; World Wide Web;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on
Conference_Location :
Canary Islands
Print_ISBN :
0-7695-1444-8
Type :
conf
DOI :
10.1109/EMPDP.2002.994279
Filename :
994279
Link To Document :
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