Single event transients in deep submicron CMOS

Author

Hass, K. Joe ; Ambles, J.W.

Author_Institution

Microelectron. Res. Center, New Mexico Univ., Albuquerque, NM, USA

Volume

1

fYear

1999

fDate

1999

Firstpage

122

Abstract

Single event transients (SET) occur when an energetic subatomic particle strikes a combinational logic element. The charge deposited by the particle causes a transient voltage disturbance, which can propagate to a storage element and be latched, resulting in single event upset (SEU). The logic design style, storage element behavior, and system timing requirements greatly impact the probability that an SET will cause an SEU. These effects are explored through circuit simulations and heavy ion testing of prototype devices

Keywords

CMOS logic circuits; VLSI; circuit simulation; ion beam effects; space vehicle electronics; timing circuits; transients; circuit simulations; combinational logic element; deep submicron CMOS; energetic subatomic particle; heavy ion testing; probability; single event transients; single event upset; storage element behavior; system timing requirements; transient voltage disturbance; Atomic measurements; CMOS logic circuits; Circuit testing; Flip-flops; Logic design; Microelectronics; Resistors; Single event upset; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867224

Filename

867224