Cadence-based simulation of floating-gate circuits using the EKV model

A simplified version of the transistor model proposed by Enz, Krummacher, and Vittoz to model FET behavior has been implemented in the popular, commercially available Cadence software package. We have expanded this model to include the drain induced barrier lowering (DIBL) effect. Several simulation experiments were performed on basic transistor circuits and compared with measured data to check the accuracy of our implementation and to explore the limitations of this modified model. We have also included some simulations of floating-gate circuits. The results of this comparison are presented in this paper and show good agreement between simulation and experimental behavior despite the simplicity of the model