Stream oriented fault tolerant array

Author

Mori, Hideki ; Tamaki, Junichi ; Uehara, Minoru

Author_Institution

Dept. of Inf. & Comput. Sci., Toyo Univ., Japan

fYear

1995

fDate

18-20 Jan 1995

Firstpage

172

Lastpage

181

Abstract

This paper describes the architecture of stream oriented fault tolerant array. Stream is a dynamically established one to one communication path among processing cells to make a wide variety of parallel applications possible. Fault tolerance is required for communication paths as well as the processor cell. Our architecture uses majority voting and cell reliability assessment. Our fault tolerant architecture ensures higher performance for parallel applications

Keywords

cellular arrays; fault tolerant computing; microprocessor chips; parallel architectures; redundancy; system recovery; wafer-scale integration; cell reliability assessment; communication paths; fault tolerant architecture; majority voting; parallel applications; stream oriented fault tolerant array; Application software; Computer architecture; Fault tolerance; Fault tolerant systems; Hardware; Manufacturing; Parallel processing; Redundancy; Timing; Voting;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-2467-6

Type

conf

DOI

10.1109/ICWSI.1995.515451

Filename

515451

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2397322