Gain error correction scheme for multiply-by-two gain amplifier in pipelined ADC

A simple scheme for correcting the gain error of multiply-by-two gain amplifiers that are used in pipelined ADC´s using analog technique is proposed. This scheme only requires a programmable capacitor array, a comparator, and a small amount of low speed digital circuitry, which can be shared between different pipelined stages. The resultant gain of two can have accuracy better than 15 bits for typical common-mode voltage error and amplifier and comparator offset voltages