Large integrated crossbar switch

Author

Naik, Rajeshwar ; Walker, D.M.H.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1995

fDate

18-20 Jan 1995

Firstpage

217

Lastpage

227

Abstract

This paper describes the design of a 256×256 port full crossbar switch for use in multiprocessor and telecommunications applications. The switch has a 50 Mbyte/sec bandwidth per port and a low message latency. Distributed arbitration is provided for output port contention. High packaging density, high speed, and I/O minimization are achieved through the use of a large area, defect-tolerant monolithic implementation in a 0.8 micron CMOS technology. The number of spare rows and columns in the switch matrix was determined by a detailed yield analysis

Keywords

CMOS digital integrated circuits; multiprocessor interconnection networks; semiconductor switches; switching circuits; telecommunication switching; 0.8 micron; 256×256 port full crossbar switch; CMOS technology; I/O minimization; defect-tolerant monolithic implementation; distributed arbitration; high packaging density; high speed operation; integrated crossbar switch; large area switch; low message latency; multiprocessor applications; output port contention; spare columns; spare rows; telecommunications applications; yield analysis; Asynchronous transfer mode; Bandwidth; CMOS technology; Control systems; Delay; Logic; Packaging; Process control; Switches; Telecommunication switching;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-2467-6

Type

conf

DOI

10.1109/ICWSI.1995.515456

Filename

515456