Title :
Defect-tolerant processor arrays
Author :
Lakkapragada, Shankar ; Walker, D.M.H.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
In this paper we describe the design and optimization of a defect tolerant MIMD processor array, for maximum performance per wafer area, targeted at applications that have a large number of operations per memory word. The optimization includes trade-offs between number of processors, amount of local memory, performance and topology of the interconnection network and yield. The yield analysis considers the use of partially good cells to increase harvest rates
Keywords :
CMOS digital integrated circuits; circuit optimisation; fault tolerant computing; integrated circuit design; integrated circuit yield; logic design; microprocessor chips; parallel architectures; reconfigurable architectures; wafer-scale integration; MIMD processor array; WSI; defect-tolerant processor arrays; interconnection network; optimization; yield analysis; Application software; Bandwidth; CMOS technology; Clocks; Computer science; Delay; Multiprocessor interconnection networks; Network topology; Packaging; Parallel processing;
Conference_Titel :
Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-2467-6
DOI :
10.1109/ICWSI.1995.515457
