• DocumentCode
    2397598
  • Title

    Yield analysis of fault-tolerant multichip module systems for massively parallel computing

  • Author

    Kim, Sungsoo ; Lombardi, Fabrizio

  • Author_Institution
    Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
  • fYear
    1995
  • fDate
    18-20 Jan 1995
  • Firstpage
    308
  • Lastpage
    317
  • Abstract
    This paper presents analytical models for evaluating the overall yield of systems manufactured using fault-tolerant multichip modules (MCMs) for massively parallel computing. In the proposed approaches, we employ a novel Markov model to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests. Several strategies for appropriately testing fault-tolerant MCMs have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRT (Least Recently Tested) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for today´s technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCMs more accurately and efficiently, thereby improving upon the reliability of the entire system
  • Keywords
    Markov processes; fault tolerant computing; integrated circuit testing; integrated circuit yield; multichip modules; parallel processing; Least Recently Tested test strategy; Markov model; fault-tolerant multichip module systems; figure of merit; massively parallel computing; redundancy; yield analysis; Analytical models; Fault tolerance; Fault tolerant systems; Multichip modules; Parallel processing; Performance analysis; Performance evaluation; Pulp manufacturing; Testing; Virtual manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-2467-6
  • Type

    conf

  • DOI
    10.1109/ICWSI.1995.515465
  • Filename
    515465