Title :
Electrical analysis of a domino logic cell with GOS faults
Author :
Renovell, M. ; Comte, M. ; Ohtake, S. ; Fujiwara, H.
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
Abstract :
Gate-oxide shorts (GOS) have an increasing impact on the integrated circuit production yield due to the reduction of the related dimensions. The detection of GOS is a challenging issue in the field of testing. This paper presents a detailed study of the impact of a GOS fault affecting a domino logic circuit. Indeed, domino logic specific clocked operating principle induces a different behavior from standard full CMOS cells under the effect of a GOS, which can enable GOS detection. Finally, some clues to enhance GOS detection in domino cells are proposed.
Keywords :
CMOS logic circuits; fault diagnosis; integrated circuit testing; logic arrays; logic testing; CMOS cells; GOS fault detection; domino logic cell; domino logic circuits; electrical analysis; gate-oxide shorts; integrated circuit production yield; CMOS logic circuits; Circuit faults; Circuit testing; Integrated circuit modeling; Logic circuits; Logic gates; MOS devices; MOSFETs; Pulse inverters; Semiconductor device modeling;
Conference_Titel :
Current and Defect Based Testing, 2005. DBT 2005. Proceedings. 2005 IEEE International Workshop on
Print_ISBN :
1-4244-0034-1
DOI :
10.1109/DBT.2005.1531299
