Title :
Towards WSI testable devices: an improved scan insertion technique
Author :
Bolchini, C. ; Buonanno, G. ; Ferrandi, F. ; Sciuto, D. ; Bombana, M. ; Cavalloro, P. ; Zaza, G.
Author_Institution :
Dipartimento di Elettronica, Politecnico di Milano, Italy
Abstract :
The aim of this paper is to introduce a different approach for the application of the partial scan methodology into a circuit to provide the most convenient solution in terms of overheads and performances. First testability analysis, based on new testability conditions, is performed to identify areas that are hard-to-test; then the partial scan technique is applied in a modified fashion only to the identified critical areas
Keywords :
design for testability; digital integrated circuits; integrated circuit design; integrated circuit testing; logic design; logic testing; wafer-scale integration; IC testing; WSI testable devices; partial scan methodology; scan insertion technique; testability analysis; Built-in self-test; Circuit analysis; Circuit testing; Costs; Design for testability; Pattern analysis; Performance analysis; Performance evaluation; System testing; Test pattern generators;
Conference_Titel :
Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-2467-6
DOI :
10.1109/ICWSI.1995.515468
