Managing high volume advanced VLSI in a manufacturing environment [MOS DRAMs]

Author

Flaherty, M. Therese

Author_Institution

Harvard Bus. Sch., Boston, MA, USA

fYear

1991

fDate

21-23 Oct 1991

Firstpage

30

Lastpage

31

Abstract

The author addresses the following questions: (1) why was improving high-volume US manufacturing performance with advanced VLSI technology during the mid and late 1980s so difficult? and (2) what can managers at all levels do to effectively and rapidly improve manufacturing performance? The conceptual arguments are illustrated with the history and experience of one US fab manager and the fab he turned around during this period. Many of the insights discussed here are drawn from, and put into context by, a four-year research historical study of 11 Japanese and 11 US fabs that manufactured integrated circuits at the 256 K DRAM level of MOS technology in high volume (greater than 10000 wafer starts a month)

Keywords

DRAM chips; MOS integrated circuits; VLSI; integrated circuit manufacture; DRAM level; MOS technology; US manufacturing performance; high volume advanced VLSI; manufacturing environment; wafer starts; Environmental management; History; Integrated circuit manufacture; Integrated circuit technology; Manufacturing automation; Manufacturing industries; Random access memory; Semiconductor device manufacture; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1991. ASMC 91 Proceedings. IEEE/SEMI 1991

Conference_Location

Boston, MA

Print_ISBN

0-7803-0152-8

Type

conf

DOI

10.1109/ASMC.1991.167377

Filename

167377