DocumentCode
2397908
Title
A 2nd Generation 32b RISC Processor with 4KByte Cache
Author
Thomas, A.R.P. ; Urquhart, J.S. ; Howard, D.W. ; Oldham, H.E. ; Furber, Steve B.
Author_Institution
Acorn Comput. Ltd., Cambridge, UK
fYear
1989
fDate
20-22 Sept. 1989
Firstpage
272
Lastpage
275
Abstract
This paper describes ΛRM3, a second generation RISC microprocessor. The device is a 32-bit CPU, with a 4KByte on-chip cache and a co-processor interface. Two asynchronous clocks are used to ensure that the speed of internal cache cycles is not compromised by the speed of the external memory system, thus permitting the device to be used with low-cost DRAMs. The chip has been fabricated on a 1.5μm DLM CMOS foundry process and prototypes have operated at over 25 MIPS peak.
Keywords
CMOS memory circuits; DRAM chips; cache storage; clocks; coprocessors; microprocessor chips; reduced instruction set computing; CPU; DLM CMOS foundry process; MIPS; asynchronous clock; coprocessor interface; low-cost DRAM; memory size 4 KByte; memory system; on-chip cache cycle; second generation RISC microprocessor; word length 32 bit; CADCAM; Central Processing Unit; Clocks; Computer aided manufacturing; Coprocessors; Costs; Logic; Microprocessors; Read-write memory; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
Conference_Location
Vienna
Print_ISBN
3-85403-101-7
Type
conf
DOI
10.1109/ESSCIRC.1989.5468057
Filename
5468057
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