Title :
CAD Tools for CORDIC IP Cores Generation
Author :
Hahanov, Vladimir ; Melnikova, Olga ; Melnik, Dmitriy ; Levchenko, Philat
Author_Institution :
Kharkov Nat. Univ. of Radio Electron., Kharkov
fDate :
Feb. 28 2006-March 4 2006
Abstract :
The paper describes the CAD tools for CORDIC IP cores generation. It gives an opportunity for user to generate fully synthesizable, verified VHDL modules, which can be further used in digital systems design.
Keywords :
digital arithmetic; hardware description languages; logic CAD; CAD tools; CORDIC IP cores generation; VHDL modules; digital systems design; Algorithm design and analysis; Circuit testing; Design automation; Design engineering; Digital systems; Equations; Graphical user interfaces; Iterative algorithms; Manufacturing industries; Silicon; CAD; CORDIC; IP Core; Test Bench; VHDL;
Conference_Titel :
Modern Problems of Radio Engineering, Telecommunications, and Computer Science, 2006. TCSET 2006. International Conference
Conference_Location :
Lviv-Slavsko
Print_ISBN :
966-553-507-2
DOI :
10.1109/TCSET.2006.4404556
