Title :
A 36-bit balanced moduli MAC architecture
Author :
Preethy, A.P. ; Radhakrishnan, D.
Author_Institution :
Div. of Comput. Eng., Nanyang Technol. Univ., Singapore
Abstract :
Recently a renewed interest is seen in RNS (Residue Number System) which stems out from the fact that these systems are inherently parallel and modular and thus are fast and simple. In many DSP applications Multiply-Accumulate (MAC) operation turns out to be the most basic one and hence an RNS based 36-bit MAC architecture is presented in this paper to speed up the whole operation. A further enhancement in speed up is achieved by exploiting the logarithmic properties of Galois fields and integer rings. The choice of forward and reverse converters used in the design results in considerable savings in silicon real estate. The adder cells used is based on pass transistor design which attribute to very low power consumption
Keywords :
Galois fields; adders; low-power electronics; multiplying circuits; residue number systems; 36 bit; DSP; Galois field; adder cell; arithmetic circuit; balanced moduli MAC architecture; forward converter; integer ring; logarithmic properties; low-power design; multiply-accumulate unit; pass transistor logic; residue number system; reverse converter; Arithmetic; Calculus; Computer applications; Computer architecture; Digital signal processing; Energy consumption; Finite impulse response filter; Galois fields; Silicon; Variable speed drives;
Conference_Titel :
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location :
Las Cruces, NM
Print_ISBN :
0-7803-5491-5
DOI :
10.1109/MWSCAS.1999.867285
