DocumentCode :
239842
Title :
Implementation of the multicast LDP protocol on the FPGA chips
Author :
Soskic, Vukota ; Smiljanic, Aleksandra ; Chicha, Zoran
Author_Institution :
Telekom Srbija, Belgrade, Serbia
fYear :
2014
fDate :
1-4 July 2014
Firstpage :
162
Lastpage :
166
Abstract :
Due to a continuous rise in Internet traffic and the appearance of new services, the use of IP protocol routing can lead to the congestion of the network resources. Because of this, the modern networks use the MPLS technology to enable support to a wide spectrum of services and make Internet traffic management more efficient. Multicast traffic is becoming more popular on the Internet, so the MPLS must efficiently support multicast traffic as well. This paper proposes the hardware implementation of the control protocol which should enable the exchange and updating of labels used for multicast traffic (mLDP). Advantage of the presented hardware implementation is that it could support higher scalability and more dynamic traffic compared to the standard, software solutions. We will examine performance of the implementation in terms of the resources that it consumes, as well as the possibilities for its further improvement.
Keywords :
Internet; field programmable gate arrays; multiprotocol label switching; routing protocols; telecommunication congestion control; transport protocols; FPGA Chips; IP protocol routing; Internet multicast traffic management; MPLS technology; control protocol hardware implementation; mLDP protocol implementation; multicast label distribution protocol; network resource congestion; Field programmable gate arrays; Hardware; Multiprotocol label switching; Ports (Computers); Routing protocols; Unicast; FPGA; labels; mLDP; mNIPLS; multicast;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Switching and Routing (HPSR), 2014 IEEE 15th International Conference on
Conference_Location :
Vancouver, BC
Type :
conf
DOI :
10.1109/HPSR.2014.6900897
Filename :
6900897
Link To Document :
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