Title :
A VLSI implementation of the VAX vector architecture
Author :
Fenwick, D. ; Redford, J. ; Stanley, T. ; Williams, D.
Author_Institution :
Digital Equipment Corp., Boxborough, MA, USA
fDate :
Feb. 26 1990-March 2 1990
Abstract :
A single-board implementation of the VAX vector architecture is described. The vector processor can be divided into three separate function units: the vector controller, implemented as a single chip; the arithmetic pipelines, implemented by four pairs of chips; and the load/store unit, implemented by one chip. In addition, the load/store chip controls a 1-MB cache. All three function units can operate independently. The vector coprocessor is designed for use in the VAX 6000 model 400 system. It was implemented using 1.5- mu m custom CMOS and LSI logics sea-of-gates gate array. Peak performance is 90 MFLOPS single precision and 45 MFLOPS double precision. The vector coprocessor achieves speedups between 3 and 40 times the scalar CPU across a range of benchmarks.<>
Keywords :
CMOS integrated circuits; DEC computers; VLSI; microcomputers; parallel architectures; 1 MB; 45 MFLOPS; 90 MFLOPS; LSI logics sea-of-gates gate array; VAX 6000 model 400 system; VAX vector architecture; VLSI implementation; arithmetic pipelines; benchmarks; cache; chips; custom CMOS; double precision; function units; load/store unit; single precision; single-board implementation; vector controller; vector coprocessor; vector processor; Arithmetic; CMOS logic circuits; Coprocessors; Large scale integration; Logic arrays; Logic gates; Pipelines; Semiconductor device modeling; Vector processors; Very large scale integration;
Conference_Titel :
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2028-5
DOI :
10.1109/CMPCON.1990.63662
