Title :
The Design of Scaled-Down Submicron 1Mb ECL/TTL BiCMOS SRAMs
Author :
Urakawa, Yukihiro ; Sato, Katsuhiko ; Matsui, Masataka
Author_Institution :
Semicond. Device Eng. Lab., TOSHIBA Corp., Kawasaki, Japan
Abstract :
This paper will describe 5V-only BiCMOS SRAM architecture covering from 0.8μm to 0.5μm design rules and its application to lM-bit ECL/ΓTL SRAMs [2,3]. Two-way BiCMOS internal voltage supply, together with newly developed interface circuits, prevents MOSFET gate-drain voltage exceeding breakdown voltage to assure MOSFET reliability, and can optimize the oxide thickness so as to minimize the gate delay.
Keywords :
BiCMOS digital integrated circuits; SRAM chips; emitter-coupled logic; transistor-transistor logic; BiCMOS; ECL; MOSFET gate-drain voltage exceeding breakdown voltage; MOSFET reliability; SRAM; TTL; emitter-coupled logic; internal voltage supply; size 0.8 mum to 0.5 mum; transistor-transistor logic; voltage 5 V; BiCMOS integrated circuits; Breakdown voltage; CMOS logic circuits; Delay; Logic design; Logic devices; Logic gates; MOSFET circuits; Random access memory; Regulators;
Conference_Titel :
Solid-State Circuits Conference, 1989. ESSCIRC '89. Proceedings of the 15th European
Conference_Location :
Vienna
Print_ISBN :
3-85403-101-7
DOI :
10.1109/ESSCIRC.1989.5468109
