Optimization and implementation of digital matched filters based on FPGA

This paper introduces the principal of digital matched filters (DMFs), and based on Field Programmable Gate Array (FPGA), we make an analysis and optimization of DMFs which used in the quick acquisition of Pseudo-Noise (PN)-code for Global Position System (GPS). A structure as “Random Access Memory (RAM)-based shift register + folded” DMF is given in this paper. Compared with traditional folded DMF, this structure utilizes the rich resources of On-chip RAM in FPGA chip to decrease the consumption of Logic Elements (LEs) in FPGA chip. With this structure, the valuable resources of LEs in FPGA chip are saved. Throughout the compilation and the timing simulation by Quartus II, we prove that the structure we proposed can acquire PN-code effectively and be reasonable in saving LEs as the implementation of DMF based on FPGA. This design of DMF can be used in GPS receivers or other Code Division Multiple Access (CDMA) receivers.