Title :
Hdl-Models Verification Strategy
Author :
Krivulya, Gennadij ; Syrevitch, Yevgeniya ; Karasev, Andrey ; Krasovskaya, Anastasiya
Author_Institution :
Kharkiv Nat. Univ. of Radioelectron., Kharkiv
fDate :
Feb. 28 2006-March 4 2006
Abstract :
Verification strategy of digital devices models, which are represented with the help of hardware description languages. The main idea stays in distinguishing sequence generation for separate functional elements, their superposition, and interactive etalon calculation.
Keywords :
formal specification; formal verification; hardware description languages; digital devices models; formal specification; functional verification; hardware description languages; interactive etalon calculation; sequence generation; Design automation; Design engineering; Digital systems; Formal languages; Hardware design languages; Input variables; Organizing; Process design; Software testing; System testing; VHDL; functional verification; graph-model; pseudo-exhaustive sequences; specification;
Conference_Titel :
Modern Problems of Radio Engineering, Telecommunications, and Computer Science, 2006. TCSET 2006. International Conference
Conference_Location :
Lviv-Slavsko
Print_ISBN :
966-553-507-2
DOI :
10.1109/TCSET.2006.4404636
