Title :
A D2-MAC/packet Equalizer
Author :
Balestro, F. ; Joanblanq, C. ; Maginot, S. ; Remy, M. ; Senn, P. ; Bernoux, J.P. ; Lanoiselée, M. ; Palicot, J. ; Veillard, J.
Author_Institution :
CNET, Meylan, France
Abstract :
The circuit presented in this paper is a high speed self-adaptive filter achieving equalization over a D2-MAC signal. It is build around a 16-tap transversal filter with a separate operative part computing the Gradient Algorithm and periodically updating the filter coefficients. This 130 000 transistors chip has been designed in a CMOS 1.0 μm technology and is at this time being used in a D2-MAC reception environment.
Keywords :
adaptive filters; equalisers; transversal filters; 16 tap transversal filter; D2 MAC signal; gradient algorithm; high speed self adaptive filter; operative part computing; packet equalizer; Bandwidth; CMOS technology; Circuits; Clocks; Equalizers; Frequency synchronization; Hafnium; Sampling methods; Signal design; Transversal filters;
Conference_Titel :
Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European
Conference_Location :
Copenhagen
Print_ISBN :
87-984232-0-7
DOI :
10.1109/ESSCIRC.1992.5468160
