An implementation of the Government Reference Architecture Waveform Developer and System Integrator roles

With the advent of the software communications architecture (SCA) for software defined radios (SDRs) and above 2 GHz (A2G) systems, the ability to develop reusable and portable software has increased significantly. Because the SCA deals primarily with GPP based software, it does not fully address all of the issues presented by A2G systems. The HC3 government reference architecture (GRA) was developed to provide an overall reference architecture for A2G systems and to extend the SCA concepts of reusability and portability into the FPGA components required by these systems. Another goal of the GRA is facilitating development of different components of the system by different developers along with allowing for an independent system integrator. The three roles defined by the GRA are the platform developer, the waveform developer and the system integrator. The hardware abstraction layer (HAL) concept is a key aspect of the GRA, bridging the gap between software/firmware (the waveform) and hardware (the platform) to allow many different waveforms to run on a single common platform while also facilitating independent development. Under an IR&D project, Raytheon teamed with L3-CSW to develop a detailed architecture and method by which a GRA programmable modem and the waveforms that run on it can be designed by cooperating parties incorporating a HAL and using the developer roles defined by the GRA. Raytheon and L3-CSW teamed to port existing A2G waveforms, including AEHF, SHF and CDL to a single modem to serve as a proof of concept and to develop the necessary architecture and methodology based on the GRA. In this paper we discuss the GRA, the HAL and how these concepts were used in a GRA-compliant implementation of multiple A2G waveforms on a single programmable modem in the context of the waveform developer and system integrator roles described by the GRA.