DocumentCode :
2400498
Title :
New micro channel features
Author :
Nicholson, James O. ; Strietelmeier, Fred E.
Author_Institution :
IBM Corp., Austin, TX, USA
fYear :
1990
fDate :
Feb. 26 1990-March 2 1990
Firstpage :
179
Lastpage :
182
Abstract :
Three features of the Micro Channel architecture are discussed. These features broaden the characteristics of that architecture to support advanced I/O devices or systems. These new features are a streaming data procedure (including 64-b transfers), address and data parity, and synchronous exception signaling. Streaming data is a procedure that provides the ability to transfer multiple data cycles within one bus envelope. The procedure distributes the device selection overhead across the total packet, nearly doubling (for 32 b) or quadrupling (for 64 b) the performance capability of the Micro Channel bus. Address and data parity are provided to improve the data integrity characteristics of the Micro Channel architecture. These mechanisms are particularly well suited to detecting typical errors, such as card seating problems, power disturbance, and electromagnetic interference. The Micro Channel architecture provides for exception signaling with the CHCK signal. The enhancements use previously reserved pins on the Micro Channel bus and retain compatibility with existing card and system board designs.<>
Keywords :
computer interfaces; 32 bit; 64 bit; CHCK signal; Micro Channel architecture; address; card seating; data parity; electromagnetic interference; power disturbance; streaming data procedure; synchronous exception signaling; Clocks; Encoding; Master-slave; Nanoscale devices; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2028-5
Type :
conf
DOI :
10.1109/CMPCON.1990.63670
Filename :
63670
Link To Document :
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