A High Performance RSA Encryption Processor in SOI and Bulk CMOS Technologies

Author

Ivey, Peter A. ; Walker, Simon N. ; Stern, Jon M. ; Davidson, Simon

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. of Sheffield, Sheffield, UK

fYear

1992

fDate

21-23 Sept. 1992

Firstpage

238

Lastpage

241

Abstract

This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of 512 bits. The chips, which are 6.2 by 4.2 millimetres and contain 50,000 gates, have been designed in a 0.7 micron CMOS, silicon on insulator process and in a 0.7 micron bulk CMOS process. The chips are functionally identical andeachform a self contained subsystem which interfaces directly to standard microprocessors. The design of the two chips was carriedout in order to directly compare the two silicon processes. SOI is found to perform 50% faster, consume 30% less power and occupy approximately the same area as the bulk device.

Keywords

CMOS integrated circuits; microprocessor chips; public key cryptography; silicon-on-insulator; SOI; bulk CMOS technologies; bulk device; high performance RSA encryption processor; public key encryption processor; standard microprocessors; word length 512 bit; Algorithm design and analysis; CMOS process; CMOS technology; Clocks; Cryptography; Galois fields; Public key; Registers; Silicon on insulator technology; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European

Conference_Location

Copenhagen

Print_ISBN

87-984232-0-7

Type

conf

DOI

10.1109/ESSCIRC.1992.5468213

Filename

5468213