A Neuron- and a Synapse Chip for Artificial Neural Networks

Author

Lansner, John A. ; Lehmann, Torsten

Author_Institution

Comput. Neural Network Center, Tech. Univ. of Denmark, Lyngby, Denmark

fYear

1992

fDate

21-23 Sept. 1992

Firstpage

213

Lastpage

216

Abstract

A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN´s):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 μm CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 μs and the weight matrix has a 10 bit resolution.

Keywords

CMOS integrated circuits; capacitors; matrix multiplication; multiplying circuits; neural chips; ANN configuration; CMOS chip set; artificial neural networks; capacitors; hardware implementations; hyperbolic tangent activation functions; matrix-vector multiplier; neuron chip; propagation time; size 2.4 mum; synapse chip; word length 10 bit; Artificial neural networks; Backpropagation algorithms; Bipolar transistors; CMOS process; Capacitors; Computer networks; Neurofeedback; Neurons; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European

Conference_Location

Copenhagen

Print_ISBN

87-984232-0-7

Type

conf

DOI

10.1109/ESSCIRC.1992.5468235

Filename

5468235