DocumentCode
2401194
Title
Interconnection failure caused by bath degradation in copper electroplating and its VM-FDC using mathematical model
Author
Imai, Shin-ichi ; Kitabata, Masaki ; Tanaka, Tomoya
Author_Institution
Semicond. Co., Manuf. Technol. Center, Panasonic Corp., Uozu, Japan
fYear
2009
fDate
10-12 May 2009
Firstpage
254
Lastpage
258
Abstract
This paper describes a copper interconnection failure in a damascene process of a system on chip (SoC) caused by the plating bath degradation in copper electroplating equipment. By ldquosemimetricsrdquo using EES (Equipment Engineering System) data for many variables in the equipment and some statistical methods, it is clarified that the root cause of the interconnection failure is the plating bath degradation. The degradation means the increase of a by-product, whose existence is confirmed by analyzing the bath plating using HPLC (high performance liquid-chromatograph). Therefore, the degradation in the plating bath causes void formation in a via hole and causes interconnection failure. Moreover, a virtual metrology (VM) model for the bath plating degradation due to the by-product is developed using a mathematical model. VM-FDC (Fault detection and classification) using a mathematical model is performed and the interconnection failure is prevented.
Keywords
electroplating; failure analysis; mathematical analysis; VM-FDC; copper electroplating; high performance liquid-chromatograph; interconnection failure; mathematical model; plating bath degradation; Copper; Data engineering; Degradation; Mathematical model; Metrology; Performance analysis; Statistical analysis; System-on-a-chip; Systems engineering and theory; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference, 2009. ASMC '09. IEEE/SEMI
Conference_Location
Berlin
ISSN
1078-8743
Print_ISBN
978-1-4244-3614-9
Electronic_ISBN
1078-8743
Type
conf
DOI
10.1109/ASMC.2009.5155995
Filename
5155995
Link To Document