Achieving supercomputer performance in a low pain environment

The hardware and software features of the MC3200 add-in board from Mercury Computer Systems are discussed. The MC3200 was designed to provide a balanced MIPS/MFLOPS engine while executing compute-intensive vector and scalar operations at high speeds. To obtain this balanced performance, the board comprises five key components: the FPU (floating-point unit), the IPU (integer processor unit), the PSU (program sequencer unit), program and data memory, and instruction cache. During a typical 100-ns clock cycle, the PSU collects an instruction from the 8K instruction cache and sends it to the IPU and FPU. The IPU uses its instructions to generate a memory address which brings a floating-point value from DRAM (dynamic RAM) and feeds the value to the FPU. The FPU loads the value into a data register and uses its three-stage pipeline and fmac instruction to provide the desired operation. The MC3200 has a C compiler and a Fortran 77 compiler and comes with an assembler. To assist in the area of debugging, the MC3200 has a disassembler and a powerful utility, called Interact. Interact serves as a subroutine and function-validating utility in which a programmer can set break points, peak and poke memory etc.<>