Testing current mode two-input logic gates

Author

Amer, S.H. ; Emara, A.S. ; El-Din, R. Mohie ; Fouad, Mohammed M. ; Madian, Ahmed H. ; Amer, Hassanein H. ; Abdelhalim, M.B. ; Draz, H.H.

Author_Institution

Electron. Eng. Dept., American Univ. in Cairo, Cairo, Egypt

fYear

2014

fDate

4-7 May 2014

Firstpage

1

Lastpage

6

Abstract

This paper focuses on the production testing of current mode logic gates using the 45nm technology. Two-input elementary gates are studied assuming five faults per transistor. It is shown that two different implementations of the same logic function might result in different minimum test sets depending on the transistor level architecture. In addition, in MCML gates, it is observed that the detection of faults in the upper PMOS load transistors is time dependent and that the test vectors that detect faults in the logic network also detect faults in the load transistors as well as the tail NMOS transistor.

Keywords

MOSFET; current-mode circuits; current-mode logic; fault diagnosis; logic circuits; logic gates; logic testing; production testing; vectors; MCML gate; current mode two-input logic gate testing; fault detection; production testing; size 45 nm; tail NMOS transistor; transistor level architecture; two-input elementary gate; upper PMOS load transistor; vector; Circuit faults; Integrated circuit modeling; Logic gates; MOS devices; Testing; Transistors; Vectors; current mode; fault model; stuck-at; testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering (CCECE), 2014 IEEE 27th Canadian Conference on

Conference_Location

Toronto, ON

ISSN

0840-7789

Print_ISBN

978-1-4799-3099-9

Type

conf

DOI

10.1109/CCECE.2014.6901052

Filename

6901052