A novel method for watermarking sequential circuits

We propose a novel technique to watermark sequential circuits by embedding a signature via state encoding. The proposed technique is a greedy heuristic for the subgraph matching problem, which has two steps: (a) watermark graph construction and (b) watermark embedding in the State Transition Graph of the FSM. Due to combinatorial complexity, reverse engineering and erasing the watermark from the FSM is not feasible with finite resources/time. The signature can be extracted by applying a specific secret sequence which is generated by the embedding algorithm. Experimental results on benchmarks chosen from IWLS´ 93 suite, show that this is a secure and flexible method for protecting sequential circuit based Intellectual Property cores.